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For a pipelines CPU with a single ALU, consider the following : A. The j + 1st instruction uses the result of jth instruction as an operand B. Conditional jump instruction C. jth and j + 1st instructions require ALU at the same time Which one of the above causes a hazard?

For a pipelines CPU with a single ALU, consider the following : A. The j + 1st instruction uses the result of jth instruction as an operand B. Conditional jump instruction C. jth and j + 1st instructions require ALU at the same time Which one of the above causes a hazard? Correct Answer A, B, C

A. Data hazards  arise when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.

B. Control hazards arise from the pipelining of branches and other instructions that change the program counter.

C. Structural hazards arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution.

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