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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6 Correct Answer 15

Key Points

It is given that there is operand forwarding. In the case of operand forwarding, the updated value from the previous instruction's PO stage is forwarded to the present instruction's PO stage. Here there's a RAW dependency between I1-I2 for R5 and between I2-I3 for R2. These dependencies are resolved by using operand forwarding as shown in the below table. The total number of clock cycles needed is 15.

CLK IF ID OF PO WO
1 I0        
2 I1 I0      
3 I2 I1 I0    
4 I3 I2 I1 I0  
5 I3 I2 I1 I0  
6 I3 I2 I1 I0  
7   I3 I2 I1 I0
8   I3 I2 I1  
9   I3 I2 I1  
10   I3 I2 I1  
11   I3 I2 I1  
12   I3 I2 I1  
13     I3 I2 I1
14       I3 I2
15         I3

clock cycles=15.

Hence the correct answer is 15.

Related Questions

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