Bissoy.com
Doctors Medicines MCQs Q&A

Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?

Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has? Correct Answer 64

Data:

Each instruction = 32 bit

Number of instructions which are supported = 70

Maximum value by unsigned operand = 8191

Formula:

Opcode

Register 1 (R)

Register 2 (R)

Immediate Operand

 

In bits,

Opcode + R + R + Immediate Operand = 32

Calculation

Number of bits needed for opcode = ⌈ log2(70)⌉ = 7 bits

The maximum value of unsigned immediate operand = 8191

2n – 1 = 8191

2n = 8192 = 213

∴ n = 13 bits

7 + R + R + 13 = 32

2R = 12

∴ R = 6 bits.

Maximum registers that a processor has = 26 = 64.

Related Questions

A processor ha s32-bit architecture. Each instruction is 1 word long (32 bits). It has 64 registers. It supports 50 instructions, which have 2 register operands + 1 immediate operand. Assuming that the immediate operand is an unsigned integer, what is its maximum value?
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
Consider the following C code. Assume that unsigned long int type length is 64 bits. unsigned long int fun (unsigned long int n) { unsigned long int i, j = 0, sum = 0 ; for (i = n; i > 1 ; i = i/2) j++ ; for ( ; j > 1 ; j = j/2) sum++ ; return (sum) ; } The value returned when we call fun with the input 240 is
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?
Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in register Ri I1: ADD R1, R2, R3 I2: MUL R7, R1, R3 I3: SUB R4, R1, R5 I4: ADD R3, R2, R4 I5: MUL R7, R8, R9 Consider the following three statements. S1: There is an anti-dependence between instructions I2 and I5 S2: There is an anti-dependence between instructions I2 and I4 S3: Within an instruction pipeline an anti-dependence always creates one or more stalls Which one of the above statements is/are correct?
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of  the  following best reflects the addressing mode implemented by this instruction for the operand in memory?
Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
Consider the following registers: 1. Accumulator and flag registers 2. B and C 3. D and E 4. H and L Which of these 8-bit registers of 8085 microprocessor can be paired together to make a 16-bit register?