An NMOS amplifier is to be designed to provide a 0.50-V peak output signal across a 50-kΩ load that can be used as a drain resistor. Using a dc supply of 3 V, what values of ID and VOV would you choose?

An NMOS amplifier is to be designed to provide a 0.50-V peak output signal across a 50-kΩ load that can be used as a drain resistor. If a gain of at least 5 V/V is needed, what value of gm is required?

A

0.1 mA/V

B

0.2 mA/V

C

0.4 mA/V

D

0.8 mA/V

An NMOS amplifier is to be designed to provide a 0.50-V peak output signal across a 50-kΩ load that can be used as a drain resistor. What W/L ratio is required if μnCox = 200 μA/V2?

A

1.23

B

1.23

C

1.43

D

1.53

An NMOS transistor is operating at the edge of saturation with an overdrive voltage VOV and a drain current ID. If is VOV is doubled, and we must maintain operation at the edge of saturation, what value of drain current results?

A

0.25ID

B

0.5ID

C

2ID

D

4ID

Various measurements are made on an NMOS amplifier for which the drain resistor RD is 20 kΩ. First, DC measurements show the voltage across the drain resistor, VRD, to be 2 V and the gate-to-source bias voltage to be 1.2 V. Then, ac measurements with small signals show the voltage gain to be −10 V/V. What is the value of Vt for this transistor?

A

0.7V

B

0.8V

C

0.9V

D

1.0V

Various measurements are made on an NMOS amplifier for which the drain resistor RD is 20 kΩ. First, DC measurements show the voltage across the drain resistor, VRD, to be 2 V and the gate-to-source bias voltage to be 1.2 V. Then, ac measurements with small signals show the voltage gain to be −10 V/V. If the process transconductance parameter is 50μA/V2, what is the MOSFET’s W/L?

A

25

B

50

C

75

D

100

An amplifier operating from ±3V provide a 2.2V peak sine wave across a 100 ohm load when provided with a 0.2V peak sine wave as an input from which 1.0mA current is drawn. The average current in each supply is measured to be 20mA. What is the amplifier efficiency?

A

20.2%

B

25.2%

C

30.2%

D

35.2%

When the voltage across the drain and the source (VDS) is increased from a small amount (assuming that the gate voltage, VG with respect to the source is higher than the threshold voltage, Vt), then the width of the induced channel in NMOS (assume that VDS is always small when compared to the Vov)

A

Will remain as was before

B

Will become non uniform and will take a tapered shape with deepest width at the drain

C

Will become non uniform and will take a tapered shape with deepest width at the source

D

Will remain uniform but the width of the channel will increase

The parallel combination of a 6.8 kΩ resistor and a 10 kΩ resistor is in series with the parallel combination of a 2.2 kΩ resistor and a 1 kΩ resistor. A 100 V source is connected across the circuit. The resistor(s) with the greatest voltage drop is (are)

A

6.8 kΩ

B

2.2 kΩ

C

6.8 kΩ and 10 kΩ

D

2.2 kΩ and 1 kΩ

What are the conditions to be satisfied by a voltage source for using it in switching regulator. i. It must supply the required output power and the losses associated with the switching regulator ii. It must be large enough to supply sufficient dynamic range line and load variations iii. It must be sufficient high to meet the minimum requirement of the regulator system to be designed iv. It may be required to store energy for a specified amount of time during power failure especially if the system is designed for a computer power supply.

A

i and iii

B

i, ii, iii and iv

C

ii, iii and iv

D

i, iii and iv

Two resistors are in series: a 5.6 kΩ resistor and a 4.7 kΩ resistor. The voltage drop across the 5.6 kΩ resistor is 10 V. The voltage across the 4.7 kΩ resistor is

A

8.39 V

B

10 V

C

2.32 V

D

0 V

An NMOS amplifier is to be designed to provide a 0.50-V peak output signal across a 50-kΩ load that can be used as a drain resistor. Using a dc supply of 3 V, what values of ID and VOV would you choose?

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