In a J-K flip flop, when Jn = 0 and Kn = 1, the output Qn + 1 will have a value of:

Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs

A

Q₁Q₀ after the 3^rd cycle are 11 and after the 4^th cycle are 00 respectively

B

Q₁Q₀ after the 3^rd cycle are 11 and after the 4^th cycle are 01 respectively

C

Q₁Q₀ after the 3^rd cycle are 00 and after the 4^th cycle are 11 respectively

D

Q₁Q₀ after the 3^rd cycle are 01 and after the 4^th cycle are 01 respectively

An X-Y flip-flop whose characteristic table is given below is to be implemented using a J-K flip-flop X Y Qn+1 0 0 1 0 1 Qn 1 0 Q̅n 1 1 0 This can be done using-

A

J = X, K = Y̅

B

J = Y, K = X̅

C

J = X̅, K = Y

D

J = Y̅, K = X

In the T-type master-slave J-K flip-flop is shown along with the clock and input waveforms. The Q_n output of flip-flop was zero initially. Identify the correct output waveform.
Electronics mcq question image

A

B

C

D

A cascaded arrangement of flip-flops, where the output of one flip flop drives the clock input of the following flip flop is known as

A

Synchronous counter

B

ripple counter

C

ring counter

D

up counter

In the J-K flip-flop, we have J = Q̅ and K = 1 as shown in the figure: Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be

A

010000

B

011001

C

010010

D

010101

A Shift register in which the output of the last flip-flop is connected to the input of the first flip-flop

A

BCD counter

B

Parallel counter

C

Ripple counter

D

Ring counter

In a down counter, which flip-flop doesn’t toggle when the inverted output of the preceeding flip-flop goes from HIGH to LOW.

A

MSB flip-flop

B

LSB flip-flop

C

Master slave flip-flop

D

Latch

The ring counter is a serial shift register with feedback from the output of the last flip-flop to the input of the first flip-flop.

A

True

B

False

What gate is placed between clock input and the input of AND gate to convert a positive level triggered flip – flop to a negative level triggered flip – flop?

A

NOR gate

B

NOT gate

C

Buffer

D

NAND gate

The functional difference between SR flip-flop and JK flip-flop is that

A

JK flip-flop is faster than SR flip-flop

B

JK flip-flop has a feed back path

C

JK flip-flop accepts both inputs 1

D

JK flip-flop does not require external clock

E

None of the above

J K	Q_n	Q_{n + 1}
0 0	0	0
0 0	1	1
0 1	0	0
0 1	1	0
1 0	0	1
1 0	1	1
1 1	0	1
1 1	1	0

In a J-K flip flop, when Jn = 0 and Kn = 1, the output Qn + 1 will have a value of:

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