Related Questions

Last year, there were three sections in a competitive exam. Out of them 33 students cleared the cut-off in Section A, 34 students cleared the cut-off in Section B and 32 students cleared the cut-off in Section C. 10 students cleared the cut-off in section A and section B, 9 cleared the cut-off in section B and section C and 8 cleared the cut-off in section A and section C. The number of students who cleared only one section was equal and was 21 for each section. How many students cleared all the three sections?
The collector supply voltage for a CE configured transistor is 10V. The resistance RL=800Ω. The voltage drop across RL is 0.8V. Find the value of collector emitter voltage.
For the given circuit, what is the minimum peak value of the output waveform if the input waveform is 10V square wave with switching time of 1 second? Assume that the input switches between +10V and -10V DC levels.
Which of the following regions of operation are mainly responsible for heating of the transistor under switching operation? 1. Saturation region 2. Cut-off region 3. Transition from saturation to cut-off 4. Transition from cut-off to saturation
Consider the following statements: 1. The voltage developed across the OFF switches of the half-bridge converter is the maximum dc-link voltage. 2. In the full-bridge converter, the voltage across the primary of the transformer is the dc link voltage. 3. The voltage developed across the OFF switches of the full-bridge converter is half the maximum dc-link voltage. Which of the above statements are correct?
A transistor is connected in CE configuration. Collector supply voltage Vcc=10V, RL=800Ω, voltage drop across RL=0.8V, α=0.96. What is base current?
Which of the following conditions must be satisfied for a transistor to be in saturation? 1. Its collector to base junction should be under forward bias 2. Its collector to base junction should be under reverse bias 3. Its emitter to base junction should be under reverse bias 4. Its emitter to base junction should be under forward bias Which of the above conditions are correct?
Given collector resistance = 2kΩ, load resistance = 5kΩ, collector capacitance = 1μF, emitter capacitance = 20μF, collector current = 2mA, source resistance = 2kΩ. If the effect of blocking capacitor is ignored, find the applicable cut-off frequency.
Consider the following statements regarding n-channel JFET: 1. The maximum drain current IDSS occurs when gate-to-source voltage VGS = 0 V and drain-to-source voltage VDS ≥ |VP|. (VP is pinch-off voltage). 2. For gate-to-source voltage VGS less than the pinch-off level, the drain current is 0 A. 3. For all levels of VGS between 0 V and the pinch-off level, the current ID will range between IDSS and 0 A, respectively. which of the above statements are correct ?
For an emitter feedback bias circuit, the value of VCC = 10V, RB = 10Kohm, RE=1Kohm and RC=2Kohm, if current flowing through collector is 0.5mA, what is the voltage difference between collector and emitter?