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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
How many cycles are used by MSP430, when reti instruction is executed?
Which of the following statements are correct? 1. Pseudo instruction is a machine instruction. 2. A pseudo instruction is an instruction to the assembler. 3. The ORG (origin) is an example of pseudo instruction. 4. It is not possible to use ORG more than once in a program. Select the correct answer using the code given below.
Why RETI instruction be the last instruction of ISR?
After RETI instruction is executed then the pointer will move to which location in the program?
With reference to 8085 microprocessor, which of the following statements are correct? 1. The DAD instruction adds the contents of the specified register pair to the contents of the DE register pair 2. The program counter is an instruction pointer 3. Whenever an instruction uses the HL pointer, the addressing is called indirect addressing. 4. HL register pair is also called data pointer
The instruction given to a computer system is loaded into the Instruction Register. The processor interprets the instruction and performs the required action. In general, these actions fall into four categories. Which of the following actions is not a part of these four categories? 
With reference to 8085 microprocessor, which of the following statements are correct? 1. INR is 1-byte instruction 2. OUT is 2-byte instruction 3. STA is 3-byte instruction
For a pipelines CPU with a single ALU, consider the following : A. The j + 1st instruction uses the result of jth instruction as an operand B. Conditional jump instruction C. jth and j + 1st instructions require ALU at the same time Which one of the above causes a hazard?
Consider the following statements
1. Dr. Sushila Tiwari Herbal Garden has been established at Muni Ki Reti in Rishikesh.
2. It is the third herbal garden in Rishikesh.
Which of the statement(s) given above is/are correct?