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Which statement(s) about IPv4 and IPv6 addresses are true?1. An IPv6 address is 32 bits long, represented in hexidecimal.2. An IPv6 address is 128 bits long, represented in decimal.3. An IPv4 address is 32 bits long, represented in decimal.4. An IPv6 address is 128 bits long, represented in hexidecimal.
Which of the following statements is/are correct? 1. An address generated by the CPU is commonly referred to as a physical address. 2. An address seen by the memory unit is commonly referred to as a logical address. 3. The run-time mapping from virtual to physical address is done by the memory management unit (MMU). Select the correct answer using the code given below.
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
With regard to computer memory, which of the following statement(s) is/are TRUE?  (A) Cache memory is 'volatile' memory. (B) Magnetic memory is 'volatile' memory.  (C) Flash memory is 'volatile' memory. (D) RAM is 'volatile' memory. Choose the correct answer from the option given below:
If the number of address bits in a memory is reduced by 2 and the addressability is doubled, the size of the memory (i.e., the number of bits stored in the memory)
A micro-instruction format has micro-ops field which is divided into three subfields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations. The size of micro-instruction is :  
Using the page table shown below, translate the physical address 25 to virtual address. The address length is 16 bits and page size is 2048 words while the size of the physical memory is four frames. Page Present (1-In, 0-Out) Frame 0 1 3 1 1 2 2 1 0 3 0 -
The semiconductor random access memory of a computer has 65,536 words, each of 8-bits. It can perform two basic operations Read and Write. How many bits are there in the Address Register of this memory?
When we use auto increment or auto decrements, which of the following is/are true? 1) In both, the address is used to retrieve the operand and then the address gets altered 2) In auto increment, the operand is retrieved first and then the address altered 3) Both of them can be used on general purpose registers as well as memory locations
To address a memory location out of N memory locations, the number of address lines required is