Bissoy.com
Doctors Medicines MCQs Q&A

When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:

When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is: Correct Answer High impedance or floating(Z)

When both pull up and pull down transistors are OFF, the high impedance for floating Z output state results.

Related Questions

In a 3-input CMOS NAND gate, the substrate terminals of NMOS transistors are grounded (lowest potential available in the circuit) and the substrate terminals of PMOS transistors are connected to VDD (maximum positive potential available in the circuit). Which of the following transistors may suffer in this circuit from the body bias effect?
When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is:
Which of the following statements are correct? (a) CMOS has a higher speed and smaller power than BJT. (b) CMOS ICs inputs should never be left unconnected as it may damage the device. (c) CMOS ICs with Schmitt trigger inputs are useful for better noise immunity. (d) CMOS is most popular logic family in VLSI Technology.
Consider the following statements regarding the Read Only Memory (ROM): 1. The stored data is lost if the power is removed. 2. It consists of an address decoder with a input lines and a programmable OR array with n output lines. 3. The minterms are ORed through the programmable switches which can be made ON or OFF to select a particular minterm. The programmable switches can be implemented by either bipolar, CMOS, nMOS or pMOS technologies. 4. Mask-programmed ROMs are used in the application where the system requires data to be stored and to be changed during the operation. Which of the above statements are not correct ?
In which of the below-mentioned logic families, the transistors operate between cut-off and active (non-saturation) states? (i) Transistor-Transistor Logic (TTL) (ii) Schottky TTL (iii) Diode Transistor Logic (DTL) (iv) Emitter Coupled Logic (ECL) Choose the correct answer from the code given below: Code:
In CMOS fabrication, nMOS and pMOS are integrated in same substrate.
The nMOS and pMOS transistors used in BiCMOS is ____________
The nMOS and pMOS transistors used in BiCMOS is . . . . . . . .
Consider the following statements about CMOS: 1. CMOS logic inverter has a maximum signal swing of 0 V to VDD. 2. The output signal swing is independent of the exact value of aspect ratio and other device parameters. 3. It is a fast switching device with wide noise margins. 4. It has zero input resistance and infinite output resistance. Which of these statements are correct?
CMOS logic dissipates _______ power than NMOS logic circuits.