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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
With reference to 8085 microprocessor, which of the following statements are correct? 1. The DAD instruction adds the contents of the specified register pair to the contents of the DE register pair 2. The program counter is an instruction pointer 3. Whenever an instruction uses the HL pointer, the addressing is called indirect addressing. 4. HL register pair is also called data pointer
Which of the following statements are correct? 1. Pseudo instruction is a machine instruction. 2. A pseudo instruction is an instruction to the assembler. 3. The ORG (origin) is an example of pseudo instruction. 4. It is not possible to use ORG more than once in a program. Select the correct answer using the code given below.
The addressing mode used in the instruction PUSH B is
Which of the following memory-based addressing mode satisfies the below statements? 1. The address of the memory location that holds the operand is included in the instruction. 2. The effective address is the address part of the instruction. 3. It is used to access the static variables.
 In which addressing mode, the operand is given explicitly in the instruction (Example instruction : ADD R4,
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of  the  following best reflects the addressing mode implemented by this instruction for the operand in memory?
Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
Some friends are traveling in a car. They were halfway to their destination before the car broke down. Now they have to push the car to reach the closest repairing shop. If 3 boys pushed the car they reach the shop in 4 hours and if 5 girls push the car then they reach the shop in 7.2 hours. How long will it take if the 2 boys and 4 girls push the car together?
A stack is implemented with an array of ‘A [0..N – 1]’ and a variable ‘pos’. The push and pop operations are defined by the following code. push(x)                 A[pos] ← x                 pos ← pos – 1 end push pop( )                 pos ← pos + 1                 return A[pos] end pop Which of the following will initialize an empty stack with capacity N for the above implementation?