What is the standard TTL noise margin ?

What is the standard TTL noise margin ? Correct Answer 0.4 V

Noise Margin: 

  • In a digital circuit, the Noise Margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.
  • For Ex: a Digital circuit might be designed to swing between 0 and 1.2 Volts, with anything below 0.2 V considered as a ‘0’ and anything above 1 Volt is considered a ‘1’. Then the noise margin for a ‘0’ would be the amount that a signal is below 0.2 Volts, and a noise margin for 1 would be the amount by which a signal exceeds 1 Volt.
  • In this case noise margins are measured as an absolute voltage, not as a ratio.
  • This is schematically explained with the help of the following diagram:

This is schematically explained with the help of the following diagram:

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A comparison of the given logic families is as shown: 

 

TTL

ECL

CMOS

Fan-In

12-14

> 10

> 10

Fan-Out

10

25

50

Power Dissipation (mW)

10

175

0.001

Noise

Margin

0.4 V

0.16 V (lowest)

1.5 V (Highest)

Propagation Delay

10

< 3 (lowest)

15 (Highest)

Noise Immunity

Very good

Good

excellent

 

Related Questions

Determine the Noise Margin for 5V TTL inverter gate: