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The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with outputs X and Y. If the initial state of the output is X = 0 and Y = 0 just before the arrival of the first clock pulse, the state of the output just before the arrival of the second clock pulse is

The circuit shown in the figure below uses ideal positive edge-triggered synchronous J-K flip flops with outputs X and Y. If the initial state of the output is X = 0 and Y = 0 just before the arrival of the first clock pulse, the state of the output just before the arrival of the second clock pulse is Correct Answer X = 1, Y = 1

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Initial state X = 0, Y = 0

When clock pulse is given, the output of the first flip flop will be toggle.

⇒ X = 1

The output of the second flip flop also get toggle.

⇒ Y = 1

When first clock pulse (or) just before the second clock pulse, X = Y = 1

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