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The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? Correct Answer C800 to CFFF

To enable 5 input AND gate: A15 A14 A̅ 13 A̅ 12 A11

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Enabling Address

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

First

1

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

Last

1

1

0

0

1

1

1

1

1

1

1

1

1

1

1

1

 

First address: 1100 1000 0000 0000 = C800

Last address: 1100 1111 111 1111 = CFFF

Range of address: C800 to CFFF

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