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Statement (I): The count-up overflow (OV) bit is 1 when the up-counter increments above the maximum positive value. Statement (II): The count-down underflow (UN) bit is 1 when the counter decrements below the minimum negative value.

Statement (I): The count-up overflow (OV) bit is 1 when the up-counter increments above the maximum positive value. Statement (II): The count-down underflow (UN) bit is 1 when the counter decrements below the minimum negative value. Correct Answer Statement (I) is true but Statement (II) is false

Concept:

Counters have status bits that are stored in word 0. Some of these bits are unique to the type of counter being programmed and some of the bits are used for all counter types.

Bit (UN): Underflow Bit

It is a count down counter only

Bit (OV): Overflow Bit

It is a count up counter only

Bit (DN): Done Bit

It is a count up and count down counter

Bit (CD): Count Down Bit

It is a count down counter only

Bit (CU): Count Up Bit

It is a count up counter only.

The following are terms associated with such counters:

  • The preset value (PRE) is the count value that the counter must accumulate before the counter output is 1.
  • The accumulated value (ACC) is the accumulated number of 0 to 1 transitions of the counter rung. The count-up (CU) enable bit is 1 when the input logic makes the up counter rung 1 and 0 when the rung is 0. The count-down (CD) enable bit is 1 when the input logic makes the down-counter rung 1 and 0 when the rung is 0.
  • The done (DN) bit is 1 for both counters when the ACC value is equal to or greater than the PRE value and 0 when it is less.
  • The count-up overflow (OV) bit is 1 when the up-counter increments above the maximum positive value.
  • The count-down underflow (UN) bit is 1 when the counter decrements below the maximum negative value.
  • Reset (RES) returns counter accumulator values to zero. As long as RES is 1, ACC and all output bits are held at 0. When RES is 0, the counter is able to start counting.

Hence from the above explanation, we can conclude that Statement (I) is true but Statement (II) is false

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