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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
Which of the following statements are correct? 1. Pseudo instruction is a machine instruction. 2. A pseudo instruction is an instruction to the assembler. 3. The ORG (origin) is an example of pseudo instruction. 4. It is not possible to use ORG more than once in a program. Select the correct answer using the code given below.
During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
A sues B to recover Rs. 1,000 alleged to be rent due under a lease executed by B. The court finds that B was in occupation of the premises during the period for which the rent is claimed, but that the alleged lease was not executed by B. At this stage A applies to amend his plaint by alleging that, though the lease was not executed by B, he is entitled to recover the amount for use and occupation of the premises.
X' executed a sale deed in favour of 'Y' on 1st January, 2002. Subsequently on 10th January, 2002, 'X' executed a sale deed in respect of the same property in favour of 'Z'. Thereafter the sale deed in favour of 'Z' executed on 10th January, 2002 was registered on 20th January, 2002. Whereas the sale deed in favour of 'Y' was registered on 30th January, 2002.
In the said case, by virtue of section 47
A register in which of the following that holds the current instruction while it is being executed is called instruction register.
A portion of the main program to call a subroutine SUB in an 8085 environment is given below. \(\begin{matrix}:\\\ :\\\ \rm LXI&\rm D,DISP\\\ \rm LP:\ \ \ \ \ CALL\ \ \ \ \ \ \ \ \ &\rm SUB\ \ \ \ \ \\\ :\\\ :\end{matrix}\) It is desired that control be returned to LP + DISP + 3 when the RET instruction is executed in the subroutine. The set of instructions that precede the RET instruction in the subroutine are:
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?
The unit that reads the instruction pool and removes the microoperations which have been executed instruction pool is