Which type of channel is formed, between P-type source, N-type substrate and P-type drain terminal, when a positive voltage is applied on the gate terminal of an enhancement type MOSFET?

The Transfer characteristic of the different types of MOSFETs is shown below, where ID is drain current and VGS is the Gate-Source voltage, the correct combination of MOSFET w.r.t to transfer characteristics is: Types of MOSFET (P) P – Channel Enhancement MOSFET (Q) P – Channel Depletion MOSFET (R) N – Channel Enhancement MOSFET (S) N – Channel Depletion MOSFET

A

P – 4, Q – 2, R – 1, S – 3

B

P – 3, Q – 2, R – 4, S – 1

C

P – 1, Q – 3, R – 2, S – 4

D

P – 2, Q – 4, R – 3, S - 1

When a negative voltage is applied on the gate terminal, a N channel is formed between N-type source, P-type substrate and N-type drain terminal of an enhancement type MOSFET.

A

True

B

False

Consider the following statements regarding n-channel JFET: 1. The maximum drain current IDSS occurs when gate-to-source voltage VGS = 0 V and drain-to-source voltage VDS ≥ |VP|. (VP is pinch-off voltage). 2. For gate-to-source voltage VGS less than the pinch-off level, the drain current is 0 A. 3. For all levels of VGS between 0 V and the pinch-off level, the current ID will range between IDSS and 0 A, respectively. which of the above statements are correct ?

A

1 and 2 only

B

1 and 3 only

C

1, 2 and 3

D

2 and 3 only

Choose the correct statement(s) i) The gate circuit impedance of MOSFET is higher than that of a BJT ii) The gate circuit impedance of MOSFET is lower than that of a BJT iii) The MOSFET has higher switching losses than that of a BJT iv) The MOSFET has lower switching losses than that of a BJT

A

Both i & ii

B

Both ii & iv

C

Both i & iv

D

Only ii

The following item consists of two statements, one labeled as the 'Statement (I)' and the other as 'Statement (II)'. Examine these two statements carefully and select the answers to these items using the codes given below: Statement (I): MOSFET is a field-effect transistor whose drain current is controlled by the voltage applied at the gate. Statement (II): MOSFET is an insulated gate FET. Codes:

A

Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)

B

Both Statement (I) and Statement (II) are individually true and Statement (II) is the correct explanation of Statement (I)

C

Both Statement (I) and Statement (II) are individually true but Statement (II) is NOT the correct explanation of Statement (I)

D

Both Statement (I) and Statement (II) are individually true but Statement (II) is NOT the correct explanation of Statement (I)

E

Statement (I) is true but Statement (II) is false

F

Statement (I) is true but Statement (II) is false

G

Statement (I) is false but Statement (II) is true

H

Statement (I) is false but Statement (II) is true

Various measurements are made on an NMOS amplifier for which the drain resistor RD is 20 kΩ. First, DC measurements show the voltage across the drain resistor, VRD, to be 2 V and the gate-to-source bias voltage to be 1.2 V. Then, ac measurements with small signals show the voltage gain to be −10 V/V. If the process transconductance parameter is 50μA/V2, what is the MOSFET’s W/L?

A

25

B

50

C

75

D

100

In a power MOSFET, pinch-off occurs when (VDS is the drain to source voltage, VGS is the gate to source voltage VT is the threshold voltage):

A

V_DS= V_GS - V_T

B

V_DS≤ V_GS - V_T

C

V_GS ≤ V_T

D

V_DS ≥ V_GS-V_T

A depletion type N channel MOSFEt with knW/L = 2 mA/V2 and Vt = 3V has its source and gate grounded. For Vd = 0.1V and neglecting channel length modulating effect. Find drain current.

A

1.18 mA

B

0.89 mA

C

0.59 mA

D

0.3 mA

Find the current through gate if the FET was given with gate to source voltage =10V and drain to source voltage =20V, the pinch off voltage was -2V and ID=2mA.

A

10mA

B

20mA

C

0mA

D

2mA

When the voltage across the drain and the source (VDS) is increased from a small amount (assuming that the gate voltage, VG with respect to the source is higher than the threshold voltage, Vt), then the width of the induced channel in NMOS (assume that VDS is always small when compared to the Vov)

A

Will remain as was before

B

Will become non uniform and will take a tapered shape with deepest width at the drain

C

Will become non uniform and will take a tapered shape with deepest width at the source

D

Will remain uniform but the width of the channel will increase

Which type of channel is formed, between P-type source, N-type substrate and P-type drain terminal, when a positive voltage is applied on the gate terminal of an enhancement type MOSFET?

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