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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
Which of the following set of instructions will lead to same result in AX register? (a) MOV AX, 0305 H OR AX, 3030 H (b) MOV AX, 0305 H ADD AX, 3030 H (c) MOV AX, 0305 H XOR AX, 3030 H (d) MOV AX, 0305 H AND AX, 3F3F H Choose the correct answer:
Which of the following statements are correct? 1. Pseudo instruction is a machine instruction. 2. A pseudo instruction is an instruction to the assembler. 3. The ORG (origin) is an example of pseudo instruction. 4. It is not possible to use ORG more than once in a program. Select the correct answer using the code given below.
The instruction that is not possible among the following is . c) MOV 55H, BL d) MOV AL, 55H
Contents of which memory location is transferred to register AL after execution of the following 8086 program? MOV CX, 2050H MOV DS, CX MOV AL, [F025]
Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line? i) Neither vectored nor multiple interrupting devices is possible. ii) Vectored interrupts is not possible but multiple interrupting devices is possible. iii) Vectored interrupts is possible and multiple interrupting devices is not possible. iv) Both vectored and multiple interrupting devices are possible.
The 8085 programming manual says that it takes seven T states to fetch and execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how long is an instruction cycle?
The instruction given to a computer system is loaded into the Instruction Register. The processor interprets the instruction and performs the required action. In general, these actions fall into four categories. Which of the following actions is not a part of these four categories? 
A computer which issues instructions in order, has only 2 registers and 3 opcodes ADD, SUB and MOV. Consider 2 different implementations of the following basic block: Case 1   Case 2 t1 = a + b;    t2 = c + d; t2 = c + d;    t3 = e – t2; t3 = e – t2;    t1 = a + b; t4 = t1 – t2;    t4 = t1 – t2;   Assume that all operands are initially in memory. Final value of computation also has to reside in memory. Which one is better in terms of memory and by how many MOV instructions?
How many times will the loop get executed in the following program? MOV CX, 05H MOV AL,01H BACK: ADD AL, AL LOOPBACK