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User level threads are threads that are visible to the programmer and are unknown to the kernel. The operating system kernel supports and manages kernel level threads. Three different types of models relate user and kernel level threads. Which of the following statements is/are true ? (a) (i) The Many - to - one model maps many user threads to one kernel thread (ii) The one - to - one model maps one user thread to one kernel thread (iii) The many - to - many model maps many user threads to smaller or equal kernel threads (b) (i) Many - to - one model maps many kernel threads to one user thread (ii) One - to - one model maps one kernel thread to one user thread (iii) Many - to- many model maps many kernel threads to smaller or equal user threads
With regard to computer memory, which of the following statement(s) is/are TRUE?  (A) Cache memory is 'volatile' memory. (B) Magnetic memory is 'volatile' memory.  (C) Flash memory is 'volatile' memory. (D) RAM is 'volatile' memory. Choose the correct answer from the option given below:
Which of the following statements is/are correct? 1. An address generated by the CPU is commonly referred to as a physical address. 2. An address seen by the memory unit is commonly referred to as a logical address. 3. The run-time mapping from virtual to physical address is done by the memory management unit (MMU). Select the correct answer using the code given below.
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
A shared variable x, initialized to zero, is operated on by four concurrent processes W, X, Y, Z as follows. Each of the processes W and X reads x from memory, increments by one, stores it to memory, and then terminates. Each of the processes Y and Z reads x from memory, decrements by two, stores it to memory, and then terminates. Each process before reading x invokes the P operation (i.e., wait) on a counting semaphore S and invokes the V operation (i.e., signal) on the semaphore S after storing x to memory. Semaphore S is initialized to two. What is the maximum possible value of x after all processes complete execution?
Which two statements describe the IP address 10.16.3.65/23?
1. The subnet address is 10.16.3.0 255.255.254.0.
2. The lowest host address in the subnet is 10.16.2.1 255.255.254.0.
3. The last valid host address in the subnet is 10.16.2.254 255.255.254.0.
4. The broadcast address of the subnet is 10.16.3.255 255.255.254.0.
Which of the following memory-based addressing mode satisfies the below statements? 1. The address of the memory location that holds the operand is included in the instruction. 2. The effective address is the address part of the instruction. 3. It is used to access the static variables.
An address space is specified by 24­bit and the correspondence memory space is 16 bit. How many words are there in memory space?
Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. What are the tag and cache line address (in hex) for main memory address (E201F)16?
An organization requires a range of IP addresses to assign one to each of its 1500 computers. The organization has approached on Internet Service Provider (ISP) for this task. The ISP uses CIDR and serves the requests from the available IP address space 202.61.0.0/17. The ISP wants to assign an address space to the organization which will minimize the number of routing entries in the ISP’s router using route aggregation. Which of the following address spaces are potential candidates from which the ISP can allot any one to the organization? I. 202.61.84.0/21 II. 202.61.104.0/21 III. 202.61.64.0/21 IV. 202.61.144.0/21