Bissoy.com
Doctors Medicines MCQs Q&A

Related Questions

On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. III. In polling, the CPU periodically checks the status bits to know if any device needs its attention. IV. During DMA, both the CPU and DMA controller can be bus masters at the same time. Which of the above statements is/are TRUE?
Consider the following statements: 1. Integral controller improves steady state response 2. By use of proportional controller, maximum peak overshoot decreases 3. Type and order of system reduces by one for derivative controller 4. Integral controller makes the system less stable in transient state due to oscillations Select the correct answer using the codes given below:
To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls
Which of the following can be adopted for the systems which does not contain DMA controller for data transmission?
In which one of the following modes does the DMA controller keep control of the bus until all the data has been transferred to (from) memory from (to) the peripheral device ?
Which of the following is a DMA controller?
Which one of the following is the correct combination of registers in DMA controller?
Which of the following of a generic DMA controller contain a base address register and an auto-incrementing counter?
Which of the following is used to transfer the data from the DMA controller to the destination?