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Consider the following interrupts for 8085 microprocessor: 1. INTR 2. RST 5.5 3. RST 6.5 4. RST 7.5 5. TRAP If the interrupt is to be non vectored to any memory location, then which of the above interrupts is/are correct?

Consider the following interrupts for 8085 microprocessor: 1. INTR 2. RST 5.5 3. RST 6.5 4. RST 7.5 5. TRAP If the interrupt is to be non vectored to any memory location, then which of the above interrupts is/are correct? Correct Answer 1 only

8085 has 5 hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR

Out of these, INTR is non vectored interrupt and remaining interrupts are vectored interrupts.

Important Points:

Interrupt

Priority

Trigger

Mask

Vector

Vectored address

Instruction

TRAP (RST 4.5)

1 (Highest)

Edge and Level

Non-maskable

Vectored

0024 H

Independent of EI and DI

RST 7.5

2

Edge

Maskable

Vectored

003C H

Controlled by EI and DI Unmasked by SIM

RST 6.5

3

Level

Maskable

Vectored

0034 H

Controlled by EI and DI Unmasked by SIM

RST 5.5

4

Level

Maskable

Vectored

002C H

Controlled by EI and DI Unmasked by SIM

INTR

5 (Lowest)

Level

Maskable

Non-Vectored

0000 to 0038 H

Controlled by EI and DI

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