Bissoy.com
Doctors Medicines MCQs Q&A

Related Questions

A computer handles several interrupt sources of which the following are relevant for this question. Interrupt from CPU temperature sensor (raises interrupt if CPU temperature is too high) Interrupt from Mouse (raises interrupt if the mouse is moved or a button is pressed) Interrupt from Keyboard (raises interrupt when a key is pressed or released) Interrupt from Hard Disk (raises interrupt when a disk read is completed) Which one of these will be handled at the HIGHEST priority?
In IC 8085 Microprocessor TRAP interrupt ISR is at which memory address?
TRAP is an interrupt in 8085. Which one of the following statements is true about the TRAP
Consider the following interrupts for 8085 microprocessor: 1. INTR 2. RST 5.5 3. RST 6.5 4. RST 7.5 5. TRAP If the interrupt is to be non vectored to any memory location, then which of the above interrupts is/are correct?
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
A microprocessor accepts external interrupts (Ext INT) through a Programmable Interrupt Controller as shown in the figure. Assuming vectored interrupt, a correct sequence of operations when a single external interrupt (Ext INT1) is received will be :
In a microprocessor, the service routine for a certain interrupt starts from a fixed location of memory which cannot be externally set, but the interrupt can be delayed or rejected. Such an interrupt is  
An 8085-microprocessor based system uses a 4K × 8 bit RAM whose starting address is AA00H. The address of the last byte in this RAM is:
In an 8085 microprocessor, which of the following is the highest priority interrupt?
Which interrupt in 8085 Microprocessor is non-maskable?