Bissoy.com
Doctors Medicines MCQs Q&A

In which addressing mode the contents of a register specified in the instruction are first decremented, and these contents are used as the effective address of the operands?

In which addressing mode the contents of a register specified in the instruction are first decremented, and these contents are used as the effective address of the operands? Correct Answer auto decrement

Index addressing mode:

In this, effective address of operand is obtained by adding the content of index register and address part of instruction.

Indirect addressing mode:

In this, address field specifies the memory location that contains effective address of operand.

Auto increment addressing mode:

 In this addressing mode, effective address is the content of register and after accessing operand, content of register is incremented.

Auto decrement addressing mode:

In this addressing mode, the contents of a register specified in the instruction are first decremented and these contents are used as effective address of operand.

Therefore option 4 is correct.

Related Questions

In which addressing mode the contents of a register specified in the instruction are first decremented, and then these contents are used as the effective address of the operands?
With reference to 8085 microprocessor, which of the following statements are correct? 1. The DAD instruction adds the contents of the specified register pair to the contents of the DE register pair 2. The program counter is an instruction pointer 3. Whenever an instruction uses the HL pointer, the addressing is called indirect addressing. 4. HL register pair is also called data pointer
In which addressing mode the effective address of the operand is the contents of a register specified in the instruction and after accessing the operand, the contents of this register is incremented to point to the next item in the list?
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of  the  following best reflects the addressing mode implemented by this instruction for the operand in memory?
Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.
Which of the following memory-based addressing mode satisfies the below statements? 1. The address of the memory location that holds the operand is included in the instruction. 2. The effective address is the address part of the instruction. 3. It is used to access the static variables.
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?