Programmable Interrupt Controller 8259A MCQ

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• In the application where all the interrupting devices are of equal priority, the mode used is
  ক

  Automatic rotation

  খ

  Automatic EOI mode

  গ

  Specific rotation

  ঘ

  EOI
• When non-specific EOI command is issued to 8259A it will automatically
  ক

  set the ISR

  খ

  reset the ISR

  গ

  set the INTR

  ঘ

  reset the INTR
• Once the ICW1 is loaded, then the initialization procedure involves
  ক

  edge sense circuit is reset

  খ

  IMR is cleared

  গ

  slave mode address is set to 7

  ঘ

  all of the mentioned
• When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a
  ক

  input to designate chip is master or slave

  খ

  buffer enable

  গ

  buffer disable

  ঘ

  none
• In a cascaded mode, the number of vectored interrupts provided by 8259A is
  ক

  4

  খ

  8

  গ

  16

  ঘ

  64
• The interrupt control logic
  ক

  manages interrupts

  খ

  manages interrupt acknowledge signals

  গ

  accepts interrupt acknowledge signal

  ঘ

  all of the mentioned
• The register that stores the bits required to mask the interrupt inputs is
  ক

  In-service register

  খ

  Priority resolver

  গ

  Interrupt Mask register

  ঘ

  None
• The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is
  ক

  Interrupt Request Register

  খ

  In-Service Register

  গ

  Priority resolver

  ঘ

  Interrupt Mask Register
• The number of hardware interrupts that the processor 8085 consists of is
  ক

  1

  খ

  3

  গ

  5

  ঘ

  7