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ln the circuit shown the device connected to Y5 can have an address in the range:

ln the circuit shown the device connected to Y5 can have an address in the range: Correct Answer FD00 - FDFF

Concept:

The simple decoder is shown below:

[ alt="F21 Tapesh S 27-5-2021 Swati D7" src="//storage.googleapis.com/tb-img/production/21/05/F21_Tapesh%20S_27-5-2021_Swati_D7.png" style="width: 227px; height: 125px;">

Input

Output

00

0001

01

0010

10

0100

11

1000

 

Addressing is done based on the inputs and their respective logic circuit connected to the address decoders.

Calculation:

In the given question the chip select for Y5 is 101.

A10A9A8 are used for that chip select so A10A9A8 = 101.

A7 ⋯ A0 are initially zeroes and at the final address these will be all 1’s.

To get the active high output for the NAND gate all the inputs must be 1 always.

The total addressing range is shown below:

[ alt="F21 Tapesh S 27-5-2021 Swati D8" src="//storage.googleapis.com/tb-img/production/21/05/F21_Tapesh%20S_27-5-2021_Swati_D8.png" style="width: 418px; height: 115px;">

FD00H to FDFFH

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