Related Questions

A NAND gate is equivalent to an AND gate followed by an inverter. All inputs must be _____ to get a low output
A low
B high
C some low and some high
D 0's
E None of the above
The NAND gate is AND gate followed by ___________.
A NOT gate
B OR gate
C AND gate
D None of the above
De Morgan's second therm says that NAND gate is equivalent to a bubbled _____ gate.
A AND
B XAND
C XOR
D OR
E None of the above
City High School must put together a debating team consisting of four debaters.There are candidates of equal ability : X,Y and Z who are all seniors; and A,B,C and D who are all juniors..The school requires that there should be two seniors and two juniors in the team.It is also necessary that all of the debaters be able to work with one another. *Debaters Y and A cannot work together. *Debaters Z and C cannot work together. *Debaters A and B cannot work together. which of the following statements must be false? 1.Debaters Y and C are never selected together. 2.Debaters Z and D are never selected together. 3.Debaters Z and D are never selected together.
A Only I
B Only II
C Only III
D All of these
There are three different roads from Shah Bag to Farm Gate and 4 different roads from Farm Gate to Banani. How many different routes are there from Shah Bag to Banani via Farm Gate?
A 4
B 3
C 12
D 7
There are three different roads from Shah Bag to Farm Gate and 4 different roads from Farm Gate to Banani. How many different routes are there Shah Bag to Banani which go through Farm Gate?
A 4
B 3
C 7
D 12
The inverter OR gate and AND gate are called decision-making elements because they can recognize some input _____ while disregarding others. A gate recognizes a word when its output is _____
A words, high
B bytes, low
C bytes, high
D character, low
E None of the above
X-OR গেইট তৈরিতে ব্যবহূত হয়- i. OR Gate ii. AND Gate iii. NOT Gate নিচের কোনটি সঠিক?
A i ও ii
B i ও iii
C ii ও iii
D i, ii ও iii
A NAND gate is called a universal logic element because
A It is used by everybody
B Any logic function can be realized by NAND gates alone
C All the minization techniques are applicable for optimum NAND gate realization
D Many digital computers use NAND gates.
When an inverter is placed between both inputs of an SR flip-flop, the resulting flip-flop is
A JK flip-flop
B D flip-flop
C T flip-flop
D Master slave JK flip-flop
E None of the above

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