What is the use of assert statement in VHDL?

What is the use of assert statement in VHDL? Correct Answer To check the consistency and generate a message

ASSERT statement is used to check the consistency of the program. It checks a condition and generates a message which is printed on the screen depending on the status of the condition whether it is true or false.

Related Questions

If NDEBUG is defined as a macro name, at the point where is included, then assert macro is defined as #define assert(ignore) ((void)0).