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Two blue flags, two red flags and four white flags are arranged in a line such that, i] the flags at the two ends of the line are of the line are of different colours. ii] no two adjacent flags or of the same colour. In how many ways can this be done?
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
Flag hoisting was done in class on Independence Day. The number of flags received by each child is 1/6 of the total number of children in the class. If the number of children was reduced to 1/3, each child would get 3 flags. How many children are there and how many flags were distributed?
Which of the following statements are correct? 1. Pseudo instruction is a machine instruction. 2. A pseudo instruction is an instruction to the assembler. 3. The ORG (origin) is an example of pseudo instruction. 4. It is not possible to use ORG more than once in a program. Select the correct answer using the code given below.
In some pipelined systems, a different instruction is used to add to numbers which can affect the flags upon execution. That instruction is _______
In Frame Check Sequence (FCS), which code is used if character length is 6 bit and generates 12 bit parity check bits?
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of  the  following best reflects the addressing mode implemented by this instruction for the operand in memory?
Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
Assume that a 12-bit Hamming codeword consisting of 8-bit data and 4 check bits is d8d7d6d5c8d4d3d2c4d1c2c1, where the data bits and the check bits are given in the following tables: Data bits d8 d7 d6 d5 d4 d3 d2 d1 1 1 0 x 0 1 0 1   c8 c4 c2 c1 Y 0 1 0 Which one of the following choices gives the correct values of x and y?
The IA-32 processor can switch between 16 bit operation and 32 bit operation with the help of instruction prefix bit.