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Assume a memory access to main memory on a cache "miss" takes 30 ns and a memory access to the cache (on a cache "hit") takes 3 ns. If 80% of the processor's memory requests results in a cache "hit", what is the average memory access time?
Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block?
Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. What are the tag and cache line address (in hex) for main memory address (E201F)16?
Consider the following statements: 1. Better memory utilization is possible with non-contiguous allocation using fixed size pages 2. Associative memory is used for providing fast access to data stored in cache memory. 3. Direct mapping of cache memory is hard to implement Which of the above statements are correct?
With regard to computer memory, which of the following statement(s) is/are TRUE?  (A) Cache memory is 'volatile' memory. (B) Magnetic memory is 'volatile' memory.  (C) Flash memory is 'volatile' memory. (D) RAM is 'volatile' memory. Choose the correct answer from the option given below:
What will happen when the data of the jQuery.cache is read from an element? b) Data is read from jQuery.cache c) Unique number is retrieved as elem & Data is read from jQuery.cache d) Data is cleared from jQuery.cache
A linear Hamming code is used to map 4-bit messages to 7-bit codewords. The encoder mapping is linear. If the message 0001 is mapped to the codeword 0000111, and the message 0011 is mapped to the codeword 1100110, then the message 0010 is mapped to
If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be __________
Consider a fully-associative data cache with 32 blocks of 64 bytes each. The cache uses LRU (Least Recently Used) replacement. Consider the following C code to sum together all of the elements of a 64 by 64 two-dimensional array of 64-bit double-precision floating point numbers. double sum (double A [64] [64] ) { int i, j ; double sum = 0 ; for (i = 0 ; i < 64; i++) for (j = 0; j < 64; j++) sum += A [i] [j] ; return sum ; } Assume all blocks in the cache are initially invalid. How many cache misses will result from the code?
What is the cache hit ratio. if memory access takes 20 ns with cache and 110 ns without it (cache uses a 10 ns memory)?