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User level threads are threads that are visible to the programmer and are unknown to the kernel. The operating system kernel supports and manages kernel level threads. Three different types of models relate user and kernel level threads. Which of the following statements is/are true ? (a) (i) The Many - to - one model maps many user threads to one kernel thread (ii) The one - to - one model maps one user thread to one kernel thread (iii) The many - to - many model maps many user threads to smaller or equal kernel threads (b) (i) Many - to - one model maps many kernel threads to one user thread (ii) One - to - one model maps one kernel thread to one user thread (iii) Many - to- many model maps many kernel threads to smaller or equal user threads
A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing ________
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________
Assume that a 12-bit Hamming codeword consisting of 8-bit data and 4 check bits is d8d7d6d5c8d4d3d2c4d1c2c1, where the data bits and the check bits are given in the following tables: Data bits d8 d7 d6 d5 d4 d3 d2 d1 1 1 0 x 0 1 0 1   c8 c4 c2 c1 Y 0 1 0 Which one of the following choices gives the correct values of x and y?
Which statement(s) about IPv4 and IPv6 addresses are true?1. An IPv6 address is 32 bits long, represented in hexidecimal.2. An IPv6 address is 128 bits long, represented in decimal.3. An IPv4 address is 32 bits long, represented in decimal.4. An IPv6 address is 128 bits long, represented in hexidecimal.
How many bits are there for random bits and error detection bits in the case of DES block ciphers?
How many redundant bits are added in block codes for k information bits and n code bits?
Nibble describes a bits combination of
Assume that a 4-bit serial in/serial out shift register is initially clear. Bits are shifted in from left. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse?
Given below are two statements:  Statement I: Minimum number of bits required to store any 3-digit decimal number is 10.  Statement II: The data in a digital computer is stored in terms of bits/ bytes where one Peta Byte is equal to 250 bits. In the light of the above statements, choose the correct answer from the options given below: