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Which of the following statements about Regular Expression is/are incorrect? A. The union of two regular expressions is also a regular expression B. The concatenation of two regular expressions is also a regular expression C. The iteration of a regular expression is also a regular expression
Consider a fully-associative data cache with 32 blocks of 64 bytes each. The cache uses LRU (Least Recently Used) replacement. Consider the following C code to sum together all of the elements of a 64 by 64 two-dimensional array of 64-bit double-precision floating point numbers. double sum (double A [64] [64] ) { int i, j ; double sum = 0 ; for (i = 0 ; i < 64; i++) for (j = 0; j < 64; j++) sum += A [i] [j] ; return sum ; } Assume all blocks in the cache are initially invalid. How many cache misses will result from the code?
Assume a memory access to main memory on a cache "miss" takes 30 ns and a memory access to the cache (on a cache "hit") takes 3 ns. If 80% of the processor's memory requests results in a cache "hit", what is the average memory access time?
What will happen when the data of the jQuery.cache is read from an element? b) Data is read from jQuery.cache c) Unique number is retrieved as elem & Data is read from jQuery.cache d) Data is cleared from jQuery.cache
Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block?
As per the RBI Act, 1934, the following functions are described as the functions of a Central Bank:
1. Banking functions
2. Advisory functions
3. Supervisory functions
4. Promotional functions
Identify the correct combination:
In designing a computer’s cache system, the cache block (or cache line) size is an important parameter. Which one of the following statements is correct in this context?
In a cache with 64-bytes cache lines, how many bits are used to determine which byte within a cache line an address points to?
Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. What are the tag and cache line address (in hex) for main memory address (E201F)16?
Consider a system with 2 level caches. Access times of Level 1 cache, Level 2 cache, and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?