A 1 to 8 demultiplexer with data input Din, address inputs S0, S1, and S2, (with S0 as the LSB) and Y̅0 to Y̅ 7 as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A0 and A1) as shown in the figure. Din, S0, S1, and S2 are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be
A 1 to 8 demultiplexer with data input Din, address inputs S0, S1, and S2, (with S0 as the LSB) and Y̅0 to Y̅ 7 as the eight de-multiplexed output, is to be designed using two 2 to 4 decoders (with enable input E and address input A0 and A1) as shown in the figure. Din, S0, S1, and S2 are to be connected to P, Q, R, and S but not necessarily in this order. The respective input connections to P, Q, R, and S terminals should be Correct Answer D<span style="position: relative; line-height: 0; vertical-align: baseline; bottom: -0.25em;font-size:10.5px;">in</span>, S<span style="position: relative; line-height: 0; vertical-align: baseline; bottom: -0.25em;font-size:10.5px;">2</span>, S<span style="position: relative; line-height: 0; vertical-align: baseline; bottom: -0.25em;font-size:10.5px;">0</span>, and S<span style="position: relative; line-height: 0; vertical-align: baseline; bottom: -0.25em;font-size:10.5px;">1</span>
The given question is the expansion of
2 : 4 decoder to 1 : 8 decoder
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We need to implement 1 : 8 DEMUX.
So, select lines of De-Mux should be mapped to address lines of the decoder.
The LSB of De-Mux should be connected to the LSB of address lines of the decoder
∴ R → S0
and S→ S1
Input to both the decoder should be same so
∴ P → Din
∴ NOT gate along with OR gate in case to select one decoder at a time so Q → S2
So,
P → Din
Q → S2
R → S0
S→ S1
Hence option (4) is correct