Structural Modeling MCQ

Test your knowledge with important Structural Modeling MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30 + more Structural Modeling MCQs at Bissoy

• What is the other name for implicit mapping?
  ক

  Nominal mapping

  খ

  Positional mapping

  গ

  Explicit mapping

  ঘ

  Inclusive mapping
• A component instantiation statement generates a(n) _______ of the component.
  ক

  Class

  খ

  Behavior

  গ

  Structure

  ঘ

  Object
• It is possible to use a GENERIC parameter as a separate component.
  ক

  True

  খ

  False
• What is the correct syntax for mapping a GENERIC parameter in structural modeling?
  ক

  label : component_name GENERIC MAP(parameter_list) PORT MAP(port_list)

  খ

  label : component_name GENERIC MAP(parameter_list)

  গ

  label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)

  ঘ

  label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
• There is a special function called interconnect () to define interconnections between pins.
  ক

  True

  খ

  False
• Which of the following is the correct order for a structural model in VHDL?
  ক

  Libraries, Entity declaration, Component declaration, Component instantiation

  খ

  Libraries, Component declaration, Entity declaration, Component instantiation

  গ

  Libraries, Entity declaration, Component instantiation, Component declaration

  ঘ

  Component declaration, Libraries, Entity declaration, Component instantiation
• It is not necessary that the order of the arguments in PORT MAP is taken as the order in which ports are declared.
  ক

  True

  খ

  False
• Which of the following is the right way to leave a port unconnected?
  ক

  L1 : my_component PORT MAP(]; a <= OPEN; ; a := OPEN; View Answer]

  খ

  L1 : my_component PORT MAP(a := OPEN);

  গ

  L1: my_component PORT MAP(a => OPEN);

  ঘ

  L1 : my_component PORT MAP(a); a := OPEN;
• The ports of a component can be left unconnected.
  ক

  True

  খ

  False
• A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?
  ক

  LABEL : my_component PORT MAP (l, m, n); ; c) LABEL : my_component PORT MAP (l => a, m => b, n => y); d) LABEL : my_component PORT MAP(a, b, y>= ]; View Answer]

  খ

  and one output(y). Which of the following statement is for the positional mapping of the component? a) LABEL : my_component PORT MAP (l, m, n); [ LABEL : my_component PORT MAP (y, a);

  গ

  LABEL : my_component PORT MAP (l => a, m => b, n => y);

  ঘ

  LABEL : my_component PORT MAP(a, b, y>= a);
• __________ mapping is less error prone.
  ক

  Port

  খ

  Positional

  গ

  Nominal

  ঘ

  Generic
• What is the property of Positional mapping?
  ক

  Easier to write

  খ

  Less error prone

  গ

  Ports can be left unconnected

  ঘ

  Difficult to write
• How many ways are there in VHDL to map the components?
  ক

  1

  খ

  2

  গ

  3

  ঘ

  4
• Which of the following function is used to map the component?
  ক

  COMPONENT INSTANTIATE

  খ

  PORT MAP

  গ

  GENERIC MAP

  ঘ

  USE
• In which part of the VHDL code, components must be declared?
  ক

  Library

  খ

  Entity

  গ

  Architecture

  ঘ

  Configuration