Pentium MCQ

Test your knowledge with important Pentium MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30 + more Pentium MCQs at Bissoy

• The results of speculative instruction execution is stored in
  ক

  visible CPU registers

  খ

  permanent memory

  গ

  temporary memory

  ঘ

  none
• The feature of Pentium II is
  ক

  high cache

  খ

  operates at 2.8 volts

  গ

  supports intel’s MMX instructions

  ঘ

  all of the mentioned
• Which of the following is not supported by Pentium-Pro?
  ক

  multiple branch prediction

  খ

  mmx instruction set

  গ

  speculative execution

  ঘ

  none
• The speed of Pentium-Pro when compared to that of Pentium is
  ক

  equal

  খ

  twice

  গ

  thrice

  ঘ

  two-third
• The unit that reads the instruction pool and removes the microoperations which have been executed instruction pool is
  ক

  fetch-decode unit

  খ

  dispatch-execute unit

  গ

  retire unit

  ঘ

  decoding unit
• The unit that performs scheduling of instructions by determining the data dependencies is
  ক

  fetch-decode unit

  খ

  dispatch-execute unit

  গ

  retire unit

  ঘ

  none
• The pool of instructions that are fetched is stored in an addressable memory called
  ক

  tristate buffer

  খ

  branch target buffer

  গ

  reorder buffer

  ঘ

  order buffer
• The microoperations that are converted by decoder are directly transferred to
  ক

  decoder register

  খ

  dispatch-execute unit

  গ

  retire unit

  ঘ

  register alias table
• The logical source(s) and logical destination(s) that the micro operation has respectively are
  ক

  2,2

  খ

  1,3

  গ

  3,1

  ঘ

  3,2
• The decoder unit in fetch-decode unit converts the instructions into
  ক

  executable statements

  খ

  machine language statements

  গ

  MMX instructions

  ঘ

  micro operations
• In fetch-decode unit, the number of parallel decoders that accept the stream of fetched instructions and decode them is
  ক

  1

  খ

  2

  গ

  3

  ঘ

  4
• The unit that accepts the sequence of instructions from the instruction cache as input is
  ক

  fetch-decode unit

  খ

  dispatch-execute unit

  গ

  retire unit

  ঘ

  none
• Which of the following is not an independent engine of Pentium-Pro?
  ক

  fetch-decode unit

  খ

  dispatch-execute unit

  গ

  control-execute unit

  ঘ

  retire unit
• The unit that is used to implement the multiple branch prediction in Pentium-Pro is
  ক

  control unit

  খ

  bus interface unit

  গ

  branch target buffer

  ঘ

  branch instruction register
• A dual independent bus has
  ক

  Enhanced system bandwidth

  খ

  CPU that can access both cache and memory simultaneously

  গ

  High throughput

  ঘ

  All of the mentioned
• The execution in which the consecutive instruction execution in a sequential flow is hampered is
  ক

  speculative execution

  খ

  out of turn execution

  গ

  dual independent bus

  ঘ

  multiple branch prediction
• The type of execution which means that the CPU should speculate which of the next instructions can be executed earlier is
  ক

  speculative execution

  খ

  out of turn execution

  গ

  dual independent bus

  ঘ

  multiple branch prediction
• Because of Pentium’s superscalar architecture, the number of instructions that are executed per clock cycle is
  ক

  1

  খ

  2

  গ

  3

  ঘ

  4
• During the execution of instructions, if an instruction is executed, then next instruction is executed only when the data is read by
  ক

  control unit

  খ

  bus interface unit

  গ

  execution unit

  ঘ

  cpu
• The instructions that pass through the fetch, decode and execution stages sequentially is known as
  ক

  sequential instruction

  খ

  sequence of fetch, decode and execution

  গ

  linear instruction sequencing

  ঘ

  non-linear instruction sequencing