Gate Logic MCQ

Test your knowledge with important Gate Logic MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30 + more Gate Logic MCQs at Bissoy

• For a pseudo nMOS design the impedance of pull up and pull down ratio is
  ক

  4:1

  খ

  1:4

  গ

  3:1

  ঘ

  1:3
• Which gate is faster?
  ক

  AND

  খ

  NAND

  গ

  NOR

  ঘ

  OR
• Which can handle high capacitance load?
  ক

  NAND

  খ

  nMOS NAND

  গ

  CMOS NAND

  ঘ

  BiCMOS NAND
• BiCMOS is used for ____ fan-out.
  ক

  less

  খ

  more

  গ

  no

  ঘ

  very less
• In CMOS NAND gate, p transistors are connected in
  ক

  series

  খ

  parallel

  গ

  cascade

  ঘ

  random
• NAND gate delay can be given as
  ক

  Ʈint

  খ

  Ʈint/n

  গ

  n*Ʈint

  ঘ

  2n*Ʈint
• As the number of inputs increases, the NAND gate delay
  ক

  increases

  খ

  decreases

  গ

  does not vary

  ঘ

  exponentially decreases
• The CMOS inverter has _____ power dissipation.
  ক

  low

  খ

  more

  গ

  no

  ঘ

  very less
• Both NAND and NOR gates can be used in gate logic.
  ক

  true

  খ

  false
• Gate logic is also called as
  ক

  transistor logic

  খ

  switch logic

  গ

  complementary logic

  ঘ

  restoring logic