Flip Flops MCQ

Test your knowledge with important Flip Flops MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30 + more Flip Flops MCQs at Bissoy

• How many flip-flops are in the 7475 IC?
  ক

  2

  খ

  1

  গ

  4

  ঘ

  8
• Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
  ক

  10.24 kHz

  খ

  5 kHz

  গ

  30.24 kHz

  ঘ

  15 kHz
• Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________
  ক

  1 kHz

  খ

  2 kHz

  গ

  4 kHz

  ঘ

  16 kHz
• Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________
  ক

  00

  খ

  11

  গ

  01

  ঘ

  10
• On a J-K flip-flop, when is the flip-flop in a hold condition?
  ক

  J = 0, K = 0

  খ

  J = 1, K = 0

  গ

  J = 0, K = 1

  ঘ

  J = 1, K = 1
• What is the significance of the J and K terminals on the J-K flip-flop?
  ক

  There is no known significance in their designations

  খ

  The J represents “jump,” which is how the Q output reacts whenever the clock goes high and the J input is also HIGH

  গ

  The letters were chosen in honour of Jack Kilby, the inventory of the integrated circuit

  ঘ

  All of the other letters of the alphabet are already in use
• A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________
  ক

  Constantly LOW

  খ

  Constantly HIGH

  গ

  A 20 kHz square wave

  ঘ

  A 10 kHz square wave
• In J-K flip-flop, “no change” condition appears when ___________
  ক

  J = 1, K = 1

  খ

  J = 1, K = 0

  গ

  J = 0, K = 1

  ঘ

  J = 0, K = 0
• The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ___________
  ক

  Parity error checking

  খ

  Ones catching

  গ

  Digital discrimination

  ঘ

  Digital filtering
• How is a J-K flip-flop made to toggle?
  ক

  J = 0, K = 0

  খ

  J = 1, K = 0

  গ

  J = 0, K = 1

  ঘ

  J = 1, K = 1
• A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________
  ক

  Two AND gates

  খ

  Two NAND gates

  গ

  Two NOT gates

  ঘ

  Two OR gates
• The characteristic of J-K flip-flop is similar to _____________
  ক

  S-R flip-flop

  খ

  D flip-flop

  গ

  T flip-flop

  ঘ

  Gated T flip-flop
• Which circuit is generated from D flip-flop due to addition of an inverter by causing reduction in the number of inputs?
  ক

  Gated JK-latch

  খ

  Gated SR-latch

  গ

  Gated T-latch

  ঘ

  Gated D-latch
• The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________
  ক

  Edge-detection circuit

  খ

  NOR latch

  গ

  NAND latch

  ঘ

  Pulse-steering circuit
• If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________
  ক

  SET

  খ

  RESET

  গ

  Clear

  ঘ

  Invalid
• What is the hold condition of a flip-flop?
  ক

  Both S and R inputs activated

  খ

  No active S or R input

  গ

  Only S is active

  ঘ

  Only R is active
• On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
  ক

  The clock pulse is LOW

  খ

  The clock pulse is HIGH

  গ

  The clock pulse transitions from LOW to HIGH

  ঘ

  The clock pulse transitions from HIGH to LOW
• When is a flip-flop said to be transparent?
  ক

  When the Q output is opposite the input

  খ

  When the Q output follows the input

  গ

  When you can see through the IC packaging

  ঘ

  When the Q output is complementary of the input
• One example of the use of an S-R flip-flop is as ____________
  ক

  Racer

  খ

  Stable oscillator

  গ

  Binary storage register

  ঘ

  Transition pulse generator
• What is one disadvantage of an S-R flip-flop?
  ক

  It has no Enable input

  খ

  It has a RACE condition

  গ

  It has no clock input

  ঘ

  Invalid State
• The S-R flip flop consist of ____________
  ক

  4 AND gates

  খ

  Two additional AND gates

  গ

  An additional clock input

  ঘ

  3 AND gates
• How many types of flip-flops are?
  ক

  2

  খ

  3

  গ

  4

  ঘ

  5
• The difference between a flip-flop & latch is ____________
  ক

  Both are same

  খ

  Flip-flop consist of an extra output

  গ

  Latches has one input but flip-flop has two

  ঘ

  Latch has two inputs but flip-flop has one
• The characteristic equation of S-R latch is ____________
  ক

  Q(n+1) = (S + Q(n))R’

  খ

  Q(n+1) = SR + Q(n)R

  গ

  Q(n+1) = S’R + Q(n)R

  ঘ

  Q(n+1) = S’R + Q'(n)R
• One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________
  ক

  The inputs of NOR latch are 0 but 1 for NAND latch

  খ

  The inputs of NOR latch are 1 but 0 for NAND latch

  গ

  The output of NAND latch becomes set if S’=0 & R’=1 and vice versa for NOR latch

  ঘ

  The output of NOR latch is 1 but 0 for NAND latch
• A NAND based S’-R’ latch can be converted into S-R latch by placing ____________
  ক

  A D latch at each of its input

  খ

  An inverter at each of its input

  গ

  It can never be converted

  ঘ

  Both a D latch and an inverter at its input
• In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is ____________
  ক

  No change

  খ

  Set

  গ

  Reset

  ঘ

  Forbidden
• What is an ambiguous condition in a NAND based S’-R’ latch?
  ক

  S’=0, R’=1

  খ

  S’=1, R’=0

  গ

  S’=1, R’=1

  ঘ

  S’=0, R’=0
• The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?
  ক

  Because of inverted outputs

  খ

  Because of triggering functionality

  গ

  Because of cross-coupled connection

  ঘ

  Because of inverted outputs & triggering functionality
• What is a trigger pulse?
  ক

  A pulse that starts a cycle of operation

  খ

  A pulse that reverses the cycle of operation

  গ

  A pulse that prevents a cycle of operation

  ঘ

  A pulse that enhances a cycle of operation