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Instruction and memory address are represented by

Instruction and memory address are represented by Correct Answer Binary codes

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On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
Which statement(s) about IPv4 and IPv6 addresses are true?1. An IPv6 address is 32 bits long, represented in hexidecimal.2. An IPv6 address is 128 bits long, represented in decimal.3. An IPv4 address is 32 bits long, represented in decimal.4. An IPv6 address is 128 bits long, represented in hexidecimal.
Which of the following memory-based addressing mode satisfies the below statements? 1. The address of the memory location that holds the operand is included in the instruction. 2. The effective address is the address part of the instruction. 3. It is used to access the static variables.
With regard to computer memory, which of the following statement(s) is/are TRUE?  (A) Cache memory is 'volatile' memory. (B) Magnetic memory is 'volatile' memory.  (C) Flash memory is 'volatile' memory. (D) RAM is 'volatile' memory. Choose the correct answer from the option given below:
In a certain number system there are only two notations to represent numbers: @ and %. 0 is represented by @ and 1 by %. The subsequent numbers are represented in the following manner: 2 is represented as %@, 3 is represented as %%, 4 is represented as %@@, 5 is represented as %@% and so on. Based on this coded language, answer the following questions: What number is represented by %%@%@%%?
Which of the following statements is/are correct? 1. An address generated by the CPU is commonly referred to as a physical address. 2. An address seen by the memory unit is commonly referred to as a logical address. 3. The run-time mapping from virtual to physical address is done by the memory management unit (MMU). Select the correct answer using the code given below.
Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of  the  following best reflects the addressing mode implemented by this instruction for the operand in memory?
Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of a constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?
A word is represented by only a set of numbers as given in any one of the alternatives. The sets of numbers given in the alternatives are represented by two classes of alphabets as shown in the given two matrices. The columns and rows of Matrix-I are numbered alternatively and represented by two classes of alphabets as shown in the given two matrices. The columns and rows of Matrix-I are numbered from 0 to 4 and that of Matrix-II are numbered from 5 to 9. A letter from these matrices can be represented first by its row and next by its column, for example, ‘C’ can be represented by 42, 56 etc and ‘P’ can be represented by 03, 65 etc. Similarly, you have to identify the set for the word ‘THRONE’.  Matrix I    Matrix II   0 1 2 3 4   5 6 7 8 9 0 H D U P F 5 J C N R G 1 O S K X I 6 P V T X L 2 R E W A Z 7 E Y W A O 3 B T Q Y N 8 K H Q U I 4 J L C V G 9 B S F M D