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Compared to CISC. RISC processors (at the same clock ) are
There are 3 clocks located at California, Berlin and Beijing respectively. If the hour hand of the clock at California is rotated by 270 degrees, then it will show same time as clock in Berlin. If the hour hand of clock in Berlin is rotated by 180 degrees, then it will show same time as clock in Beijing. If time at clock at Beijing is 8 : 30 PM what time is clock at California showing?
The RISC architecture is preferred to CISC because RISC architecture has
A clock strikes once at 1 o'clock, twice at 2 o'clock and thrice at 3 o'clock, and so on. If it takes 12 seconds to strike at 5 o'clock, what is the time taken by it to strike at 10 o'clock?
A clock strikes once at 1 O'clock, twice at 2 O'clock twice at 2 O'clock, thrice at 3 O'clock and so on. How many times will it strike in 24 hours
Three friends converted the time of 24 hours clock in that of 12 hour clock as follows: Name of the children Time in 24 hour clock Time in 12 hour clock Cheeku 23:45 11:45 pm Bittu  16:30 04:30 am Pinki 19:28 07:28 pm Who has shown incorrect time in 12 hour clock?
A clock rings once in 1 O' clock, twice in 2 O' clock and thrice in 3 O' clock and so on, then how much time the clock ring in a day (24 hours)?
Assume that 1. the hour and minute hands of a clock move without jerking. 2. the clock shows a time between 8 o'clock and 9 o'clock 3. the two hands of the clock are one above the other. After how many minute (nearest integer) will the two hands be again lying one above the other?
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
The number of CPIs(Clock Per Instruction) for an instruction of RISC processors is