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The following are some events that occur after a device controller issues an interrupt while process L is under execution? (P) The processor pushes the process status onto the control stack. (Q) The processor finishes the execution of the current instruction. (R) The processor executes the interrupt service routine. (S) The processor pops the process status of from the control stack. (T) The processor loads the new PC value based on the interrupt. Which one of the following is the correct order in which the events above occur?
Assume that we test the performance of two processors, P1 and P2, on a program. We find the following about each: Processor P1 has a CPI of 2 and executes 2 billion instructions per second. Processor P2 has a CPI of 1 and executes 8 billion instructions per second. Which processor has higher performance on this program? (Recall that CPI stands for Cycles Per Instruction.)
Study the information carefully and answer the questions given below: If we arrange the alphabets in the word "RATE" in the English alphabetical order, word "AERT" is formed. Then the third alphabet from the left in this word is "R". similarly, from the word "OPEN" we get - "ENOP" and the third alphabet from the left is "O". From the word "CHEF" we get - "CEFH" the third alphabet from the left "F". From the word "TOY" we get - "OTY" and the third alphabet from the left is "Y". From the word "EAT" we get - "AET" and the third alphabet from the left is "T" If we use all these letters, then a meaningful English word "FORTY" can be formed. Now find which of the following word set DOES NOT give a meaningful word in a similar way.
Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many registers the processor has?
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } What is the minimum number of registers needed in the instruction set architecture of the processor to compile this code segment without any spill to memory? Do not apply any optimization other than optimizing register allocation.
Which of the following are true? A. Desktop computer is a general-purpose computer made up of a separate monitor, keyboard, mouse and processor unit B. Laptop is where monitor, keyboard, pointing device, processor unit are combined in a single device C. Tablet is a device with a touch screen; which has a virtual keyboard which uses touch screen technology D. Smart Watch is a device that uses CRT technology so that the screen can bend around the wrist E. Mainframe computer runs small application where small data need to be processed Choose the correct answer from the options given below:
The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment. c = a + b; d = c * a; e = c + a; x = c * c; if (x > a) {     y = a * a; } else {      d = d * d;      e = e * e; } Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code?
Consider the following processor design characteristics. I. Register-to-register arithmetic operations only II. Fixed-length instruction format III. Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?
Which of the following takes the processor, when the processor enters the BDM mode?
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T?