Signal Descriptions of 80286 MCQ

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• The signal that causes the 80286 to perform the processor extension interrupt while executing the WAIT and ESC instructions are
  ক

  BUSY (active low)

  খ

  PEACK (active low)

  গ

  PEREQ

  ঘ

  ERROR (active low)
• To filter the output, a 0.047microfarads, 12V capacitor is connected between the pins
  ক

  CAP and ground

  খ

  Output pin and ground

  গ

  CAP and Vcc

  ঘ

  NMI and ground
• The minimum number of clock cycles required in an input pulse width of the RESET pin is
  ক

  4

  খ

  2

  গ

  8

  ঘ

  16
• The pin that is used to insert wait states in a bus cycle is
  ক

  WAIT

  খ

  BHE (active low)

  গ

  READY (active low)

  ঘ

  WAIT(active low)
• The LOCK (active low) is activated automatically by hardware using
  ক

  XCHG signal

  খ

  Interrupt acknowledge

  গ

  Descriptor table access

  ঘ

  All of the mentioned
• If M/IO (active low) signal is ‘0’ then it indicates
  ক

  I/O cycle

  খ

  Memory cycle

  গ

  I/O cycle or INTA cycle

  ঘ

  I/O cycle or HALT cycle
• The signals S1 (active low), S2 (active low) are
  ক

  output signals

  খ

  indicate initiation of bus cycle

  গ

  define type of bus cycle with M/IO (active low)

  ঘ

  all of the mentioned
• The 8 address lines, A23-A16 of 80286 are zero during
  ক

  memory transfer

  খ

  address transfer

  গ

  memory to processor transfer

  ঘ

  I/O transfer
• The clock frequency applied at the CLK pin is internally divided by
  ক

  2

  খ

  4

  গ

  8

  ঘ

  1
• The 80286 is available in the package as
  ক

  68-pin PLCC (plastic leaded chip carrier)

  খ

  68-pin LCC (lead less chip carrier)

  গ

  68-pin PGA (pin grid array)

  ঘ

  all of the mentioned