Semiconductor Memory Interfacing MCQ

Test your knowledge with important Semiconductor Memory Interfacing MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30 + more Semiconductor Memory Interfacing MCQs at Bissoy

• If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
  ক

  RAM

  খ

  ROM

  গ

  RAM and ROM

  ঘ

  ONLY RAM
• If (address line) Ao=0 then, the status of address and memory are
  ক

  address is even and memory is in ROM

  খ

  address is odd and memory is in ROM

  গ

  address is even and memory is in RAM

  ঘ

  address is odd and memory is in RAM
• To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
  ক

  parallel

  খ

  serial

  গ

  both serial and parallel

  ঘ

  neither serial nor parallel
• In most of the cases, the method used for decoding that may be used to minimise the required hardware is
  ক

  absolute decoding

  খ

  non-linear decoding

  গ

  linear decoding

  ঘ

  none
• In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
  ক

  lower address memory bank

  খ

  even address memory bank

  গ

  static lower memory bank

  ঘ

  odd address memory bank
• In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
  ক

  upper address memory bank

  খ

  even address memory bank

  গ

  static upper memory

  ঘ

  odd address memory bank
• If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
  ক

  512

  খ

  1024

  গ

  2048

  ঘ

  none
• To address a memory location out of N memory locations, the number of address lines required is
  ক

  log N (to the base 2)

  খ

  log N (to the base 10)

  গ

  log N (to the base e)

  ঘ

  log (2N) (to the base e)
• If a location is selected, then all the bits in it are accessible using a group of conductors called
  ক

  control bus

  খ

  address bus

  গ

  data bus

  ঘ

  either address bus or data bus
• The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
  ক

  one dimensional

  খ

  two dimensional

  গ

  three dimensional

  ঘ

  none