Processes and Sequential Statements MCQ

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• Which of the following is a conditional statement for VHDL?
  ক

  Entity

  খ

  Wait

  গ

  If

  ঘ

  Process
• If any entity is defined as inout it can be both read and written.
  ক

  True

  খ

  False
• The wait statement “wait on” uses which type of data type?
  ক

  BIT

  খ

  BIT_VECTOR

  গ

  Sensitivity-list

  ঘ

  Boolean
• The wait statement “wait until” uses which type of data type?
  ক

  BIT

  খ

  BIT_VECTOR

  গ

  Integer

  ঘ

  Boolean
• In which part of a VHDL code, the components are declared?
  ক

  Process

  খ

  Architecture

  গ

  Entity

  ঘ

  Begin
• Which one of the following is not a right syntax of wait statement?
  ক

  Wait on

  খ

  Wait for

  গ

  Wait until

  ঘ

  Wait at
• Which of the following is the function of “wait” statement of VHDL?
  ক

  To take a short break from the program

  খ

  To wait until any subroutine specified is completed

  গ

  To terminate the program

  ঘ

  To redirect the direction flow of the program to another direction
• Which one of the following keyword is used to define a process in VHDL?
  ক

  “process”

  খ

  “proc”

  গ

  “pr”

  ঘ

  “pro”