Logic Design MCQ

Test your knowledge with important Logic Design MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30 + more Logic Design MCQs at Bissoy

• Which of the following is a conditional statement for VHDL?
  ক

  Entity

  খ

  Wait

  গ

  If

  ঘ

  Process
• If any entity is defined as inout it can be both read and written.
  ক

  True

  খ

  False
• The wait statement “wait on” uses which type of data type?
  ক

  BIT

  খ

  BIT_VECTOR

  গ

  Sensitivity-list

  ঘ

  Boolean
• The wait statement “wait until” uses which type of data type?
  ক

  BIT

  খ

  BIT_VECTOR

  গ

  Integer

  ঘ

  Boolean
• In which part of a VHDL code, the components are declared?
  ক

  Process

  খ

  Architecture

  গ

  Entity

  ঘ

  Begin
• Which one of the following is not a right syntax of wait statement?
  ক

  Wait on

  খ

  Wait for

  গ

  Wait until

  ঘ

  Wait at
• Which of the following is the function of “wait” statement of VHDL?
  ক

  To take a short break from the program

  খ

  To wait until any subroutine specified is completed

  গ

  To terminate the program

  ঘ

  To redirect the direction flow of the program to another direction
• Which one of the following keyword is used to define a process in VHDL?
  ক

  “process”

  খ

  “proc”

  গ

  “pr”

  ঘ

  “pro”
• Which one of the following is an exponentiation operator in VHDL?
  ক

  ^

  খ

  *

  গ

  **

  ঘ

  @
• Which one of the following is not a library unit?
  ক

  Package

  খ

  Entity

  গ

  Bit_Vector

  ঘ

  Architecture
• Which one of the following we can’t declare in a process?
  ক

  Variable

  খ

  Bit

  গ

  Constant

  ঘ

  Integer
• Which of the following describes the structure of a VHDL code correctly?
  ক

  Library Declaration; Configuration; Entity Declaration; Architecture Declaration

  খ

  Library Declaration; Entity Declaration; Configuration; Architecture Declaration

  গ

  Library Declaration; Configuration; Architecture Declaration; Entity Declaration

  ঘ

  Library Declaration; Entity Declaration; Architecture Declaration; Configurations
• Which of the following VHDL design units contain the description of the circuit?
  ক

  Configurations

  খ

  Architecture

  গ

  Entity

  ঘ

  Library
• Which among the following wait statement execution causes the enclosing process to suspend and then wait for an event to occur on the signals?
  ক

  Wait until Clk = ‘1’

  খ

  Wait on x, y, z

  গ

  Wait on clock until answer > 80

  ঘ

  Wait for 12 ns
• On which technology, the modern CAD systems are based on?
  ক

  ICG

  খ

  GCI

  গ

  GIF

  ঘ

  IFG
• Which one of the following commands draws a rectangle?
  ক

  ARC

  খ

  POL

  গ

  REC

  ঘ

  CO
• Which key combination is used to obtain properties palette in AutoCAD?
  ক

  Ctrl + 1

  খ

  Ctrl + 2

  গ

  Ctrl + 3

  ঘ

  Ctrl + 4
• How many types of CAD softwares are there?
  ক

  2

  খ

  3

  গ

  4

  ঘ

  5
• Which of the following languages is a hardware definition language?
  ক

  VHDL

  খ

  C

  গ

  C++

  ঘ

  Assembly language
• Which of the following tools simulates function for small digital systems?
  ক

  Schematic Capture

  খ

  SimUaid

  গ

  Test Generation

  ঘ

  PC board layout
• Which one of the following is the main purpose of the tool “Simulation”?
  ক

  Generating PLA/PAL designing files for PLD designers

  খ

  Creating and editing logic diagrams for logic design

  গ

  Generating minimized logic equations

  ঘ

  Resolving errors and critical timing problems before any hardware is actually built
• Which one of the following is the main purpose of event-driven simulation?
  ক

  To eliminate unnecessary gate simulations without introducing an unacceptable amount of additional testing

  খ

  To get the count of errors occurred during simulation

  গ

  To set a blueprint of the logic circuit

  ঘ

  To get the count of logic gates used inside the circuitry
• How are the state transition graphs presented during simulation and testing?
  ক

  Using triangular pulse

  খ

  Using sine pulse

  গ

  Using rectangular pulse

  ঘ

  Using spikes
• Which one of the following is not a part of testing of sequential circuits?
  ক

  Observation of the outputs

  খ

  Verification of state tables

  গ

  Defining voltage levels at input or output

  ঘ

  Using the direct set and clear inputs, set the flip-flop states to correspond to one of the present states in the table
• What is a “unit delay model”?
  ক

  A model where the total propagation delay is unit

  খ

  A model where the propagation delay of every element is assumed as unity

  গ

  A model where there is no propagation delay

  ঘ

  A model where there is 2 units of propagation delay totally
• Which one of the following is a possible result of simulation of sequential circuits?
  ক

  Digital bits

  খ

  Graphs

  গ

  Timing diagrams

  ঘ

  Current and voltages
• Which one of the following best describes “simulation” for sequential circuits?
  ক

  Creating a PCB layout of the circuit

  খ

  Designing the circuit on software only

  গ

  Designing and observe the working of the circuit by virtually running it

  ঘ

  Writing a VHDL code for the circuit
• By which one of the following, the vertical and horizontal directions of an FPGA are separated?
  ক

  Line

  খ

  Channel

  গ

  Strobe

  ঘ

  Discs
• Which of the following is related to a characteristic of FPGA?
  ক

  PLD

  খ

  EPROM

  গ

  EEPROM

  ঘ

  RAM
• What is the full form of UCS in AutoCAD?
  ক

  User Cooperation Server

  খ

  User Controlled Server

  গ

  User Coordinate System

  ঘ

  User Controlled System