Features of Pentium 4, Netburst Microarchitecture For Pentium4 -1 MCQ

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• After the micro-ops are issued by the microcode ROM, the control goes to
  ক

  trace cache

  খ

  front end branch predictor

  গ

  execution module

  ঘ

  instruction decoder
• If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
  ক

  microcode ROM

  খ

  front end branch predictor

  গ

  execution module

  ঘ

  instruction decoder
• The unit that predicts the locations from where the next instruction bytes are fetched is
  ক

  trace cache

  খ

  front end branch predictor

  গ

  execution module

  ঘ

  instruction decoder
• Trace cache can store the micro-ops upto a range of
  ক

  6 K decoded micro-ops

  খ

  8 K decoded micro-ops

  গ

  10 K decoded micro-ops

  ঘ

  12 K decoded micro-ops
• The unit that does not store the instructions, but the decoded stream of instructions is
  ক

  trace cache

  খ

  front end branch predictor

  গ

  microcode ROM

  ঘ

  none
• In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to
  ক

  trace cache

  খ

  front end branch predictor

  গ

  microcode ROM

  ঘ

  none
• The unit that decodes the instructions concurrently and translate them into micro-operations is
  ক

  trace cache

  খ

  instruction decoder

  গ

  execution module

  ঘ

  front end branch predictor
• The front module of Pentium 4 consists of
  ক

  trace cache

  খ

  microcode ROM

  গ

  front end branch predictor

  ঘ

  all of the mentioned
• Which of the following is not a module of Pentium 4 architecture?
  ক

  front end module

  খ

  execution module

  গ

  control module

  ঘ

  none
• The feature of Pentium 4 is
  ক

  works based on NetBurst microarchitecture

  খ

  clock speed ranges from 1.4GHz to 1.7GHz

  গ

  has hyper-pipelined technology

  ঘ

  all of the mentioned