Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction MCQ

Test your knowledge with important Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction MCQ and their applications. These MCQs are beneficial for competitive exams too. Explore 30+ more Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction MCQs on Bissoy. Bissoy App

• The branch target buffer is
  ক

  four-way set-associative memory

  খ

  has branch instruction address

  গ

  has destination address

  ঘ

  all of the mentioned
• The memory device that holds branch target addresses for previously executed branches is
  ক

  Tristate buffer

  খ

  RAM

  গ

  ROM

  ঘ

  Branch target buffer
• The CPU has to wait until the execution stage to determine whether the condition is met in
  ক

  unconditional branch

  খ

  conditional branch

  গ

  pipelined execution branch

  ঘ

  none of the mentioned
• The architecture in which the hardware decides which instructions are to be issued concurrently at run time is
  ক

  super pipelined architecture

  খ

  multiple instruction issue

  গ

  very long instruction word architecture

  ঘ

  superscalar architecture
• The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in
  ক

  super pipelined architecture

  খ

  multiple instruction issue

  গ

  very long instruction word architecture

  ঘ

  super scalar architecture
• Which of the following is a class of architecture of MII (multiple instruction issue)?
  ক

  super pipelined architecture

  খ

  multiple instruction issue

  গ

  very small instruction word architecture

  ঘ

  super scalar architecture
• For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
  ক

  super pipelined technique

  খ

  multiple instruction issue

  গ

  super pipelined technique and multiple instruction issue

  ঘ

  none of the mentioned
• The speed of integer arithmetic of Pentium is increased to a large extent by
  ক

  on-chip floating point unit

  খ

  superscalar architecture

  গ

  4-stage pipelines

  ঘ

  all of the mentioned
• Which of the following is a cache of Pentium?
  ক

  data cache

  খ

  data cache and instruction cache

  গ

  instruction cache

  ঘ

  none of the mentioned
• The number of stages of the integer pipeline, U, of Pentium is
  ক

  2

  খ

  4

  গ

  3

  ঘ

  6
• The salient feature of Pentium is
  ক

  superscalar architecture

  খ

  superpipelined architecture

  গ

  superscalar and superpipelined architecture

  ঘ

  none of the mentioned