Dynamic RAM Interfacing MCQ

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• If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes the range of time it may take then, refresh time (tr) can be defined as
  ক

  n*td

  খ

  td/n

  গ

  n/td

  ঘ

  tdn
• A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold data charge level practically constant is
  ক

  constant timer

  খ

  data managing timer

  গ

  refresh timer

  ঘ

  qualitative timer
• The number of memory chips that are enabled at a time for refresh activity is
  ক

  2

  খ

  4

  গ

  8

  ঘ

  more than 1
• Memory refresh activity is
  ক

  initialised by processor

  খ

  initialised by external bus master

  গ

  initialised by refresh mechanism

  ঘ

  initialised either by processor or by external bus
• The field in which dynamic RAM is more complicated than static RAM is
  ক

  complexity

  খ

  interfacing circuit

  গ

  execution unit

  ঘ

  cost
• The process of refreshing the data in the RAM to reduce the possibility of data loss is known as
  ক

  data cycle

  খ

  regain cycle

  গ

  retain cycle

  ঘ

  refresh cycle
• To store the charge as a representation of data, the basic dynamic RAM cell uses
  ক

  resistor

  খ

  capacitor

  গ

  diode

  ঘ

  transistor
• If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires
  ক

  1 transistor along with capacitance

  খ

  2 transistors along with resistance

  গ

  3 transistors along with diode

  ঘ

  2 transistors along with capacitance
• Whenever a large memory is required in a microcomputer system, the memory subsystem is generally designed using
  ক

  Static RAM

  খ

  Dynamic RAM

  গ

  Both static and dynamic RAM

  ঘ

  ROM
• The advantage of dynamic RAM is
  ক

  high packing density

  খ

  low cost

  গ

  less power consumption

  ঘ

  all of the mentioned