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Higher Study | Computer Organization and Architecture | Instruction Pipelining

Pipelining 1. Reduces clock period of long combinational operations. 2. Allows large combinational functions to be broken down into pieces whose delays are balanced with the rest of the system components.
A particular parallel program computation requires 100 sec when executed on a single processor. If 40% of this computation is inherently sequential (i.e. will not benefit from additional processors), then theoretically best possible elapsed times of this program running with 2 and 4 processors, respectively, are
On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.     Initialize the address register     Initialize the count to 500 LOOP: Load a byte from device     Store in memory at address given by address register     Increment the address register     Decrement the count     If count! = 0 go to LOOP Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions? Instruction Meaning of instruction I0 : MUL R2, R0, R1 R2← R0 * R1 I1 : DIV R5, R3, R4 R5 ← R3 / R4 I2 : ADD R2, R5, R2 R2 ← R5 + R2 I3 : SUB R5, R2, R6 R5 ← R2 – R6
Which of the following hazards occurs if the read takes place before the write operation is complete?
Reduced Instruction Set Computer (RISC) is based on which of the following architectures?
Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence?
Which of the following instruction processing activity of the CPU can be pipelined? 1. Instruction encoding 2. Operand loading 3. Operand storing
Which one of the following is false about Pipelining?
The register which contains the instruction that is to be executed is known as
Consider the following data path diagram.   Consider an instruction: R0 ← R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively. 1. R2r, TEMP1f, ALUadd, TEMP2w 2. R1r, TEMP1w 3. PCr, MARw, MEMr 4. TEMP2r, R0w 5. MDRr, IRw Which one of the following is the correct order of execution of the above steps?  
Consider a control unit generating the control signals. These control signals are divided into five mutually exclusive groups as shown below: Groups  G1  G1  G1  G1  G1 Control  Signals   3  7  10  12  2 How many bits are saved using the Vertical Micro-programmed instead of Horizontal Micro-programmed control unit?
A data-driven machine is one that executes an instruction if the needed data is available. The physical ordering of the code listing does not dictate the course of execution. Consider the following pseudo-code 1) Multiply E by 0.5 to get F 2) Add A and B to get E 3) Add B with 0.5 to get D 4) Add E and F to get G 5) Add A with 10.5 to get C Assume A, B, C are already assigned values and the desired output is G Which of the following sequence of execution is valid?
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